CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 161
Figure 2-62. TLB/XTLB Refill Exception Handling (1/2)(a) Handling TLB/XTLB Refill Exceptions (Hardware)
BD bit0BD bit1
EPCPC4
EXL1
EPCPC
Kernel mode is set and interrupts are disabled.
= 1 (bootstrap)= 0 (Normal)
Check for multiple exceptions
EntryHiVPN2, ASID
X/ContextVPN2
Set Cause register (ExcCode, CE)
To guideline to TLB/XTLB exception handler
Start
Yes
EXL = 1?
(SR1)
No
NoYes Instruction
in branch delay
slot?
BEV
PCFFFF FFFF 8000 0000H + vector offset
(Unmapped, cacheable space)
PCFFFF FFFF BFC0 0200H + vector offset
(Unmapped, uncached space)
XTLB Refill
Vector offset = 080H
TLB Refill
Vector offset = 000H
TLB Refill
Vector offset = 180H
NoYes XTLB
Exception?
M16 = 1?
(config20)
No
Instruction
in dela
y
slot?
BD bit1
EPCPC-4
EPCEIM
BD bit0
EPCPC
EPCEIM
NoYes
Yes