CHAPTER 5 ETHERNET CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 285
5.2.2 En_MACC1 (MAC Configuration Register 1)Bits Field R/W Default Description
31:12 Reserved R/W 0 Reserved for future use. Write 0s.
11 TXFC R/W 0 Transmit flow control enable:
Setting this bit to a ‘1’ enables to transmit the pause control frame.
10 RXFC R/W 0 Receive flow control enable:
Setting this bit to a ‘1’ enables MAC Control Block to execute PAUSE
operation for the pause time on the setting of the pause timer. The setting of
the pause timer must be updated every time a valid PAUSE control frame is
received regardless of the setting of this bit.
9 SRXEN R/W 0 Receive enable:
Setting this bit to a ‘1’ enables the function of the MAC Address field filtering.
8 PARF R/W 0 Control packet pass:
Setting this bit to a ‘1’ allows MAC Control Block to check for all received
packets including control frames. When this bit is set to a ‘0’, MAC control
block does not check the reception of a control frame.
7 PUREP R/W 0 Pure preamble:
Setting this bit to a ‘1’ allows the recognition of start of a new packet only
when a pure preamble (“0101” only) is captured.
6 FLCHT R/W 0 Length field check:
When this bit is set to a ‘1’, MAC Control Block compares the length field
value in the packet to the actual packet length, and indicates the result in the
status vector. When this bit is set 0, MAC does not check the Frame length
field.
5NOBO R/W0No Back Off:
When this bit is set to a ‘1’, MAC Control Block always transmits the packet
with no back off operation.
4 Reserved - - Reserved for future use. Write a 0.
3 CRCEN R/W 0 CRC append enable:
Setting this bit to a ‘1’ enables MAC to append calculated CRC code to the
end of transmitted packet automatically.
2 PADEN R/W 0 PAD append enable:
Setting this bit to a ‘1’ enables MAC control block to append PAD when the
transmitted packet length is less than 64 octets because the input data (TPD)
length is less than 60 bytes before appending the CRC.
1 FULLD R/W 0 Full duplex enable:
Setting this bit to a ‘1’ enables the full duplex operation.
0 HUGEN R/W 0 Large packet enable:
Setting this bit to a ‘1’ enables MAC to transmit and receive a packet of which
length is over the value of En_LMAX register.