APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary Users Manual S15543EJ1V0UM 517
LWL Load Word Left (3/3) LWL
Given a doubleword in a register and a doubleword in memory, the operation of LWL is as follows:
B C D E F GA H
J K L M N OI P
Register
Memory

LWL

vAddr2..0 Destination Type Offset
(LEM)
0
1
2
3
4
5
6
7
SSSSPFGH
SSSSOPGH
SSSSNOPH
SSSSMNOP
SSSSLFGH
SSSSKLGH
SSSSJKLH
SSSSIJKL
0
1
2
3
0
1
2
3
0
0
0
0
4
4
4
4
Remark
LEM
Little-endian memory (BigEndianMem = 0)
Type
AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset
pAddr2..0 sent to memory

S

sign-extend of destination bit 31
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception