CHAPTER 5 ETHERNET CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 307
Operation flow for receive packet
i) Prepares the receive buffer descriptors
ii) Initializes registers (RXVDP, RXE)
iii) Reads the receive buffer descriptor
iv) Waits for exceeding of receive drain threshold (RXDRTH)
v) Writes receive data to data buffer by using master DMA burst operation
vi) Increments the Receive Descriptor Pointer if the current data buffer is full
vii)Check out the RNOD
If the remaining number of descriptors is less than four times of the alert level, generates an interrupt to
request an adding descriptor.
viii)Reads the next buffer descriptor
ix) Stores the received data
x) Stores the receive status in the last buffer descriptor (L = 1)
xi) Generates an interrupt for the end of reception
xii)Reads next receive descriptor if available
How to add the receive buffer descriptors
i) Prepares the receive buffer descriptors
ii) Sets the number of buffer descriptors in En_RXPDR as well as the alert level
iii) Generates an interrupt by this Ethernet Controller
iv) Adds the receive buffer descriptors in the memory
v) Sets the number of buffer descriptors in En_RXPDR as well as the alert level
5.3.6 Address Filtering
The Ethernet Controller can parse a destination address in a received packet. The destination address is filtered
using the condition in En_AFR register set by VR4120. The condition for unicast, multicast and broadcast can be
configured independently.
(1) Unicast address filtering
The destination address in a received packet is compared with the station address in En_LSA1 and En_LSA2
registers. When both the addresses are equal, the received packet is accepted. The comparison is executed for every
received packet.
(2) Multicast address filtering
Two filtering methods are supported. With one method, all of received multicast packets are accepted when PRM
bit in En_AFR register is set to a ‘1’.
With the other method, received multicast packets are filtered, using a hash table configured by the values in
En_HT1 and En_HT2 registers. At first, the CRC is executed against the multicast destination address in the received
packet using following polynomial expression.
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Bits [28:23] of the CRC calculation result are decoded. When the bits in En_HT1 and En_HT2 registers pointed by
the decoded result are equal to ‘1’, the received packet with the multicast destination address is accepted. In order to
set the En_HT1 and En_HT2 registers, CRCs for multicast destination address to be received should be calculated
before receiving any multicast packet.