CHAPTER 2 VR4120A
170 Preliminary User’s Manual S15543EJ1V0UM
Figure 2-67. Instruction Cache Line Format
22 21
VPTag
0
122
Data
0
Data
Data
Data
31
PTag : Physical tag (bits 31 to 10 of physical address)
V: Valid bit
Data : Cache data
2.7.2.2 Organization of the data cache (D-cache)
Each line of D-cache data has an associated 25-bit tag that contains a 22-bit physical address, a Valid bit, a Dirty
bit, and a Write-back bit.
The VR4120A Core D-cache has the following characteristics :
write-back
direct-mapped
indexed with a virtual address
checked with a physical tag
organized with a 4-word (16-byte) cache line.
Figure 2-68 shows the format of a 4-word (16-byte) D-cache line.
Figure 2-68. Data Cache Line Format
WVD PTag
Data
Data
24 23 22 21 0
063
111 22
W : Write-back bit (set if cache line has been written)
D: Dirty bit
V: Valid bit
PTag : Physical tag (bits 31 to 10 of physical address)
Data : D-cache data