NEC uPD98502 - page 391

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 391
7.5.2 P_PLBA (PCI Lower Base Address Register)
When the PCI Controller issues 32-bit PCI address, this register contains PCI base address. When the access
from Internal bus-side to PCI-side comes, the PCI Controller replaces the upper 10 bits of the address on internal bus
with the upper 10 bits of this register, and issues as the address on PCI bus.
R/WBits Field
Internal
bus
PCI
Default Description
31:0 PLBA R/W
(upper
10 bits)
R
(lower
22 bits)
R/W
(upper
10 bits)
R
(lower
22 bits)
0 PCI lower base address.
Upper 10 bits are readable/writeable.
Lower 22 bits are read-only.
7.5.3 P_IBBA (Internal Bus Base Address Register)
This register contains internal bus base address. When the access from PCI-side to internal bus-side comes, the
PCI Controller replaces the upper 10-bits of the address on PCI with the upper 10-bits of this register, and issues as
the address on internal bus.
R/WBits Field
Internal
bus
PCI
Default Description
31:0 IBBA R/W
(upper
10 bits)
R
(lower
22 bits)
R/W
(upper
10 bits)
R
(lower
22 bits)
0 Internal bus base address.
Upper 10 bits are readable/writeable.
Lower 22 bits are read-only.
7.5.4 P_VERR (Version Register)
This register contains the version number of the PCI Controller. The upper 16 bits indicate the major version, and
the lower 16 bits indicate the minor version.
R/WBits Field
Internal
bus
PCI
Default Description
31:0 VERR R/W
(upper
10 bits)
R
(lower
22 bits)
R/W
(upper
10 bits)
R
(lower
22 bits)
0001_
0000H
Hardwired to “0001_0000H”, which indicates the current version
of The PCI Controller.