CHAPTER 1 INTRODUCTION
44 Preliminary Users Manual S15543EJ1V0UM
1.7.7.2 UTOPIA data interface
Pin Name Pin No. I/O Active Level Function
CLKUSL0 T4 I UTOPIA clock select
CLKUSL1 T3 I (CLKUSL1/0 = L/L: 33 MHz, H/L: 25 MHz, L/H: 16.5 MHz)
UDRCLK AK11 O Receive clock
UDRCLV AH9 I H Receive cell available
UDRE_B AJ8 O L Receive enable
UDRSC AG9 I H Receive cell start
UDRAD0 AK13 O Receive PHY address
UDRAD1 AG13 O Receive PHY address
UDRAD2 AF13 O Receive PHY address
UDRAD3 AK12 O Receive PHY address
UDRAD4 AJ11 O Receive PHY address
UDRD0 AG11 I Receive data
UDRD1 AF11 I Receive data
UDRD2 AK10 I Receive data
UDRD3 AJ10 I Receive data
UDRD4 AH10 I Receive data
UDRD5 AK9 I Receive data
UDRD6 AJ9 I Receive data
UDRD7 AK8 I Receive data
UDTCLK AK16 O Transmit clock
UDTCLV AH11 I H Transmit cell available
UDTE_B AK14 O L Transmit enable
UDTSC AH14 O H Transmit cell start position
UDTAD0 AG16 O Transmit PHY address
UDTAD1 AH16 O Transmit PHY address
UDTAD2 AG15 O Transmit PHY address
UDTAD3 AF15 O Transmit PHY address
UDTAD4 AK15 O Transmit PHY address
UDTD0 AK19 O Transmit data
UDTD1 AG18 O Transmit data
UDTD2 AH18 O Transmit data
UDTD3 AK18 O Transmit data
UDTD4 AH17 O Transmit data
UDTD5 AJ17 O Transmit data
UDTD6 AK17 O Transmit data
UDTD7 AF16 O Transmit data