APPENDIX A MIPS III INSTRUCTION SET DETAILS
454 Preliminary Users Manual S15543EJ1V0UM
BGTZ Branch On Greater Than Zero BGTZ
rs

BGTZ

0 0 0 1 1 1

0
0 0 0 0 0 offset
31 26 25 21 20 16 15 0
655 16
Format:
BGTZ rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. If the contents of general register
rs
are zero or greater when
compared to zero, then the program branches to the target address, with a delay of one instruction.
Operation:
32 T: target (offset15)14 || offset || 02
condition (GPR [rs] 31 = 0) and (GPR [rs] 032)
T+1: if condition then
PC PC + target
endif
64 T: target (offset15)46 || offset || 02
condition (GPR [rs]63 = 0) and (GPR [rs] 064)
T+1: if condition then
PC PC + target
endif
Exceptions:
None