NEC uPD98502 Table 2-22. Operation in Each Stage of Pipeline (MIPS III)

CHAPTER 2 VR4120A
86 Preliminary User’s Manual S15543EJ1V0UM
Table 2-22. Operation in Each Stage of Pipeline (MIPS III)
Cycle Phase Mnemonic Description
IF
Φ
1 IDC Instruction cache address decode
ITLB Instruction address translation
Φ
2 ICA Instruction cache array access
ITC Instruction tag check
RF
Φ
1 IDEC Instruction decode
Φ
2 RF Register operand fetch
BAC Branch address calculation
EX
Φ
1 EX Execution stage
DVA Data virtual address calculation
SA Store align
Φ
2 DCA Data cache address decode/array access
DTLB Data address translation
DC
Φ
1 DLA Data cache load align
DTC Data tag check
DTD Data transfer to data cache
WB
Φ
1 DCW Data cache write
WB Write back to register file