NEC uPD98502 - page 284

CHAPTER 5 ETHERNET CONTROLLER
284 Preliminary User’s Manual S15543EJ1V0UM
5.2.1.4 Interrupt and configuration registers
These register control interrupt occur and configuration for this block.
Table 5-5. Interrupt and Configuration Registers Map
Offset Address Register Name R/W Access Description
1000_m234H En_CCR R/W W Configuration Register
1000_m238H En_ISR RC W Interrupt Service Register
1000_m23CH En_MSR R/W W Mask Serves Register
Remarks 1. In the “Offset Address” field and in the “Register Name” field,
Ethernet Controller #1: m = 2, n = 1,
Ethernet Controller #2: m = 3, n = 2
2. In the “R/W” field,
“W” means “writeable”,
“R” means “readable”,
“RC” means “read-cleared”,
“- “ means “not accessible”.
3. All internal registers are 32-bit word-aligned registers.
4. The burst access to the internal regi ster is prohibited.
If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU.
5. Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read
response data with the data-error bit set on SysCMD [0] is returned.
6. Write access to the reserved area will set the CBERR bit in the NSR register, and the write data is lost.
7. In the “Access” filed,
“W” means that word access is valid,
“H” means that half word access is valid,
“B” means that byte access is valid.
8. Write access to the read-only register cause no error, but the write data is lost.
9. The CPU can access all internal registers, but IBUS master device cannot access them.