NEC uPD98502 PCI-Host PCI Contr oller, Internal Contr oller

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 385
7.3.4.2 Transition by power management event
The sequence is as follows:
1. When Power Management Event occurs, the VR4120A writes a ‘1’ to PMERQ bit in P_PPCR register.
2. The PCI Controller asserts PME_B if PME_En bit in PMCSR register is enabled.
3. An external PCI-Host device writes a ‘1’ to PME_Status bit in PMCSR register or writes a ‘0’ to PME_En bit in
PMCSR register in order to clear PME_B.
4. The PCI Controller deasserts PME_B.
Hereafter, as same case of the transition is issued by PCI-Host.
Figure 7-11. The Sequence of the Transition by PME
Same with the case that PCI-Host requests the transition of the power state
clear PME#
by writing '1' to PME_Status
bit in PMCSR register
or by making PME_En bit '0'
in PMCSR register disabled
assert PME#
if PME_En b it in PMCSR
register is enabled
deassert PME#
write '1' to PM ERQ
in PPCR register
write
write
PCI-Host PCI
Contr oller
Internal
Contr oller