CHAPTER 1 INTRODUCTION
Preliminary Users Manual S15543EJ1V0UM 55

1.11 Interrupts

The controller supports maskable interrupts and Non-Maskable to the CPU.

Figure 1-12. Interrupt Signal Connection

USB Controller
Ethernet Co ntroller #1
ATM Cell Processor
System Controller VR4120A
S_ISR
intb[0]
intb[1]
intb[2]
intb[4]
intb[3]
EXTNMI
EXTINT
nmib
S_IMR
BUS-IF
UART
TIMER
Ethernet Co ntroller #2
S_NSR
S_NER
DSU
BUS-IF
PCI Controller