CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 139
2.5.3.8 WatchLo (18) and WatchHi (19) registers
The VR4120A processor provides a debugging feature to detect references to a selected physical address; load
and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception.
Figures 2-55 and 2-56 show the format of the WatchLo and WatchHi registers.
Figure 2-55. WatchLo Register Format
29
321031
PAddr0 0 R W
111
WatchLo Register
PAddr0 : Specifies physical address bits 31 to 3.
R : If this bit is set to 1, an exception will occur when a load instruction is executed.
W : If this bit is set to 1, an exception will occur when a store instruction is executed.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
Figure 2-56. WatchHi Register Format
32
031
0
WatchHi Register
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.