CHAPTER 7 PCI CONTROLLER
394 Preliminary User’s Manual S15543EJ1V0UM
7.5.8 P_IIMR (Internal Bus Interrupt Mask Register)IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bitposition to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is resetto ‘0’, the corresponding bit of the IGSR is masked. If it is set to ‘1’, the corresponding bit is unmasked. When themask bit is reset and the bit in IGSR is set, the PCI Controller sets the interrupt signal to the VR4120A.
R/WBits Field
Internal
bus
PCI
Default Description
31:16 IUINT R/W R/W 0 Mask bits for the Interrupts defined by the system the chip is
used.
‘0’ means masked.
‘1’ means unmasked.
15:12 Reserved - - 0 Hardwired to ‘0H’.
11 PINTR R/W R/W 0 Mask bit for the PCI interruption
‘0’ means masked.
‘1’ means unmasked.
10 PSERI R/W R/W 0 Mask bit for the PCI SERR#
‘0’ means masked.
‘1’ means unmasked.
9 PPERR R/W R/W 0 Mask bit for PCI Parity Error
‘0’ means masked.
‘1’ means unmasked.
8 PPREQ R/W R/W 0 Mask bit for the state transition for PPMI.
‘0’ means masked.
‘1’ means unmasked.
7 SRREQ R/W R/W 0 Mask bit for the Software Reset issue.
‘0’ means masked.
‘1’ means unmasked.
6 IRBER R/W R/W 0 Mask bit for internal bus Error in read transaction.
‘0’ means masked.
‘1’ means unmasked.
5 IWBER R/W R/W 0 Mask bit for internal bus Error in write transaction.
‘0’ means masked.
‘1’ means unmasked.
4 IFDSC R/W R/W 0 Mask bit for the discard of data in internal bus FIFO.
‘0’ means masked.
‘1’ means unmasked.
3 RDTAT R/W R/W 0 Mask bit for PCI Target Abort in read transaction.
‘0’ means masked.
‘1’ means unmasked.
2 WRTAT R/W R/W 0 Mask bit for PCI Target Abort in write transaction.
‘0’ means masked.
‘1’ means unmasked.
1 RDMAT R/W R/W 0 Mask bit for PCI Master Abort in read transaction.
‘0’ means masked.
‘1’ means unmasked.
0 WRMAT R/W R/W 0 Mask bit for PCI Master Abort in write transaction.
‘0’ means masked.
‘1’ means unmasked.