NEC uPD98502 424 , CHAPTER 9 TIMER 9.1 Overview, 9.2 Block Diagram

424 Preliminary User’s Manual S15543EJ1V0UM
CHAPTER 9 TIMER
9.1 Overview
There are two Timers. The timers are clocked at the system clock rate. All two timers are read/writeable by the
CPU. Timers can be read by the CPU while they are counting. They can be automatically reloaded with the “Timer Set
Count Register” value and restarted. Two timers issues interrupt to the CPU upon reaching their maximum value, the
interrupts can be enabled/disabled.
The TM0IS and TM1IS fields in the Interrupt Status Register “S_ISR” indicate the end of timer count, when set
indicate there is a timer event that completed. All timers count down. The read-write registers “TM0CSR” or
“TM1CSR” have different offset from the read register so write registers are not affected while a value is read from the
read registers “TM0CCR”/”TM1CCR” which indicate a running count of the timer/counter at a given time. Once a value
is loaded in the TM0CSR/TM1CSR, it stays there until Timer’s interrupts are cleared in the Interrupt Status Register
“S_ISR”. The original value can be reloaded in the counter to restart it from that count if Timer CH0/CH1 reload enable
bit is set in the Timer Mode Register “TMMR”. Interrupts are automatically cleared upon CPU reading the Interrupt
Status Register of System Controller “S_ISR”.
9.2 Block Diagram
to S_ISR
TM0CSR
TM1CSR
TM0CCR
TM1CCR
CH0 DOWN COUNTER
TMMR
CH1 DOWN COUNTER
to S_ISR
to CPU
from CPU
from CPU
to CPU
from CPU
to CPU
CPU Clock
100 MHz/66 MHz