NEC uPD98502 - page 377

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 377
7.2.2.3 Write issue from PCI to Internal bus
(1) Posted write transaction
If PPWRD bit in P_BCNT register is ‘0’, the PCI Controller uses “Posted Write Transaction” rule for write
transactions from Internal bus-side to PCI-side. The rule is as follows;
<1> A PCI master device issues the write transaction to an internal bus target block.
<2> The PCI Controller accepts this access and stores the write data into the internal FIFO. The transaction on
PCI bus is completed at this moment. Then, the PCI Controller issues “retry” for all of write access to all PCI
write transaction to the PCI Controller until the transaction on internal bus has been completed.
<3> The PCI Controller issues the write transaction to the internal bus target block
<4> The internal bus target block accepts this access and the PCI Controller completes the write transaction to
it. After the completion of the transaction, the PCI Controller can accepts the new write access on PCI bus
again.
Figure 7-6. Posted Write Transaction from PCI to Internal bus
PCI
Controller
PCI
Master
Device
Internal
Bus Block
<1>
<2>
<3>
<4>
The maximum burst size is 16 words, and when more than 16 words write burst is issued on PCI bus, the PCI
Controller accepts it and issues “disconnect” at 16th word. When the PCI Controller encounters the address boundary,
it issues “disconnect”, too.
When the PCI Controller receives Bus Error on Internal bus after it has accepted posted-write from PCI-side, the
PCI Controller sets IWBER bit of P_IGSR register and PWBER bit of P_PGSR register, and reports by interrupts to
PCI-Host and the VR4120A (if not masked). The data in the internal FIFO will be discarded.