NEC uPD98502 - page 378

CHAPTER 7 PCI CONTROLLER
378 Preliminary User’s Manual S15543EJ1V0UM
(2) Non posted write transaction
When PPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write
transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word.
The rule is as follows;
<1> PCI master device issues the write transaction to an internal bus target block.
<2> The PCI Controller responds to this access by asserting DEVSEL_B and latches the first word of the burst
data. However, the PCI Controller does not assert TRDY_B at this moment.
<3> The PCI Controller issues the write transaction to the internal bus target block.
<4> The internal bus target block accepts this access and the PCI Controller writes the first word which is
latched to it.
<5> The PCI Controller asserts TRDY_B in order to indicate that first data phase is completed. Then, the PCI
Controller issues “disconnect” to PCI master device when it issues the burst transfer. PCI master device
should terminates the transaction as soon as possible.
Figure 7-7. Non Posted Write Transaction from PCI to Internal bus
PCI
Controller
PCI
Master
Device
Internal
Bus Block
<1>
<4>
<2>
<3>
<5>
When the PCI Controller receives Bus Error on Internal bus, it completes the first data phase by asserting TRDY_B
and issues “disconnect” to PCI master device if it issues the burst transfer. Then, the PCI Controller sets IWBER bit of
P_IGSR register and PWBER bit of P_PGSR register and issues interrupts to an external PCI-Host device and the
VR4120A (if not masked). The data in the internal FIFO will be discarded.