NEC uPD98502 CHAPTER 2 VR4120A, 2.1 Overview for VR4120A

Preliminary User’s Manual S15543EJ1V0UM 57
CHAPTER 2 VR4120A
Caution The µ
µµ
µ PD98502 doesn’t support MIPS16 instructions.
This chapter describes an VR4120A RISC Processor Core operation (MIPS instruction, Pipeline, etc.). Following in
this Document, it is call for VR4120A RISC Processor Core with “VR4120A” or “VR4120A Core” simply.
2.1 Overview for VR4120A
Figure 2-1 shows the internal block diagram of the VR4120A core.
In addition to the conventional high-performance integer operation units, this CPU core has the full-associative
format translation look aside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even)
for one entry. Moreover, it also has instruction caches, data caches, and bus interface.
Figure 2-1. VR4120A Core Internal Block Diagram
CPUCP0Instruction
Cache
16 Kbyte
Data
Cache
8 Kbyte
Bus
Interface
Clock
Generator
Address/Data(o)
Address/Data(i)
ID bus
VA bus
Control(o)
Control(i)
TLB
System
Controller
VR4120A Core