CHAPTER 2 VR4120A
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2.5 Exception Processing
This chapter describes VR4120A CPU exception processing, including an explanation of hardware that processes
exceptions.
2.5.1 Exception processing operation
The processor receives exceptions from a number of sources, including translation lookaside buffer (TLB) misses,
arithmetic overflows, I/O interrupts, and system calls. When the CPU detects an exception, the normal sequence of
instruction execution is suspended and the processor enters Kernel mode (see Section 2.4 Memory Management
System for a description of system operating modes).
The processor then disables interrupts and transfers control for execution to the exception handler (located at a
specific address as an exception handling routine implemented by software). The exception handler saves the
context of the processor, including the contents of the program counter, the current operating mode (User or
Supervisor), statuses, and interrupt enabling. This context is saved so it can be restored when the exception has
been serviced.
When an exception occurs, the CPU loads the Exception Program Counter (EPC) register with a location where
execution can restart after the exception has been serviced. The restart location in the EPC register is the address of
the instruction that caused the exception or, if the instruction was executing in a branch delay slot, the address of the
branch instruction immediately preceding the delay slot.
The VR4120A processor supports a Supervisor mode and high-speed TLB refill for all address spaces. The
VR4120A CPU also provides the following functions:
Interrupt enable (IE) bit
Operating mode (User, Supervisor, or Kernel)
Exception level (normal or exception is indicated by the EXL bit in the Status register)
Error level (normal or error is indicated by the ERL bit in the Status register).
Interrupts are enabled when the following conditions are satisfied:
2.5.1.1 Interrupt enable
An interrupt is enabled when the following conditions are satisfied.
•Interrupt enable bit (IE) = 1
•EXL bit = 0, ERL bit = 0
•Corresponding IM field bits in the Status register = 1
2.5.1.2 Operating mode
The operating mode is specified by KSU bit in the Status register when both the exception level and error level are
normal (0). The operation enters Kernel mode when either EXL bit or ERL bit in the Status register is set to 1.
2.5.1.3 Exception/error levels
Returning from an exception resets the exception level to normal (0) (for details, see APPENDIX A MIPS III
INSTRUCTION SET DETAILS).
The registers that retain address, cause, and status information during exception processing are described in
Section 2.5.3 Exception processing registers. For a description of the exception process, see Section 2.5.4
Details of exceptions.