CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 205
3.4.3 Memory signal connections
µ
µµ
µ
PD98502
SMD[31:0]
SRMOE_B
SRMCS_B
SDRAS_B
SDCS_B
SDCAS_B
SDWE_B
SDCLK[1:0]
SMA[20:0]
SDQM[3:0]
SDCKE[1:0]
(SDQM=SMA[17:14])
FlashPROM
OE_B
WE_B
CS_B
A[20:0] D[31:0]
SDRAM
RAS_B
CS_B
CAS_B
WE_B
DQM[3:0]
CKE
CLK[1:0]
DQ[31:0]A[13:0]
ADDRESS
DATA
SMA[20:0]
SMD[31:0]
SMA[20:0]
SMD[31:0]
Table 3-3. External Pin Mapping
External Pin Access to ROM Access to SDRAM
Name Bits
SMA [13:0] A[13:0] A[13:0]
[17:14] A[17:14] SDQM[3:0]
[20:18] A[20:18]
SMD [31:0] D[31:0] DQ[31:0]
SDCS_B --- SDCS_B
SDRAS_B --- SDRAS_B
SDCAS_B --- SDCAS_B
SDWE_B SDWE_B SDWE_B
SDCKE [1:0] --- SDCKE[1:0]
SDCLK [1:0] --- SDCLK[1:0]
SRMCS_B SRMCS_B ---
SRMOE_B SRMOE_B ---
RMSL [1:0] --- ---
Remark RMSL signal determines boot memory data bus size.