NEC uPD98502 - page 223

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 223
3.5.4 ITCNTR (IBUS Timeout Timer Control Register)
The IBUS Timeout Timer control register “ITCNTR” is a read-write and word-aligned 32-bit register. ITCNTR is
used to enable use of the IBUS Timeout Timer. ITCNTR is initialized to 0H at reset and contains the following field:
Bits Field R/W Default Description
31:1 Reserved R/W 0 Hardwired to 0.
0 ITWEN R/W 0 IBUS Timeout Timer enable
1 = Enable
0 = Disable
3.5.5 ITSETR (IBUS Timeout Timer Set Register)
This register sets the cycle for Deadman’s Switch functions. The Deadman’s Switch cycle can be set in 1-clock
increments in a range from 1 to 232–1 clock. The DSUCLRR’s DSWCLR bit must be set by means of software within
the specified cycle time. ITSETR is a 32-bit word-aligned register. Default is 8000_0000H.
Bits Field R/W Default Description
31:0 ITTIME R/W 8000_
0000H
IBUS Timeout value setting
Timeout = ITTIME value system clock period (100 MHz:10 ns, 66 MHz:15 ns)
example:
ITTIME = 05F5_E100H (100 MHz) or 03F9_40AAH (66 MHz)
-> Timeout = 1 sec
ITTIME = 0BEB_C200H (100 MHz) or 07F2_8154H (66 MHz)
-> Timeout = 2 sec
ITTIME = 11E1_A300H (100 MHz) or 0BEB_C200H (66 MHz)
-> Timeout = 3 sec
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