APPENDIX A MIPS III INSTRUCTION SET DETAILS
488 Preliminary Users Manual S15543EJ1V0UM
DSRAV Doubleword Shift Right Arithmetic Variable DSRAV
rs
SPECIAL
0 0 0 0 0 0 rt rd 0
0 0 0 0 0

DSRAV

0 1 0 1 1 1

31 26 25 21 20 16 15 11 10 6 5 0
6 5 555 6
Format:
DSRAV rd, rt, rs
Description:
The contents of general register
rt
are shifted right by the number of bits specified by the low-order six bits of
general register
rs
, sign-extending the high-order bits. The result is placed in register
rd
.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
64 T: s GPR [rs]5..0
GPR [rd] (GPR [rt]63)s || GPR [rt] 63..s
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)