CHAPTER 2 VR4120A
162 Preliminary User’s Manual S15543EJ1V0UM
Figure 2-62. TLB/XTLB Refill Exception Handling (2/2)(b) Servicing TLB/XTLB Refill Exceptions (Software)
•The occurrence of TLB Refill, TLB Invalid, and TLB
Modified exceptions is disabled by using an unmapped space.
•The occurrence of the Watch and Interrupt exceptions is
disabled by setting EXL= 1.
•Other exceptions are avoided in the OS programs.
•However, the Cold Reset, Soft Reset, and NMI exceptions
are enabled.
Execute MFC0 instruction
X/Context register
ERET
Servicing by each exception routine
•The execution of the ERET instruction is disabled in the
branch delay slots for other jump instructions.
•The processor does not execute an instruction in the branch
delay slot for the ERET instruction.
•PC ← EPC, EXL ← 0
•The physical address for a virtual address that is loaded into
the Context register is loaded into the EntryLo register and written
to the TLB.
•As long as a data/instruction address exists in the mapping
space, another TLB Refill exception may occur. In such
a case, EXL = 1 is set, causing a jump to the common
exception vector. (In this case, the common exception handler
handles the TLB miss, the ERET instruction returns control to
the user program, then a TLB Refill exception is generated
again.)