NEC uPD98502 - page 167

CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 167
2.6.3.2 Privilege mode
The VR4120A supports three system modes: kernel expanded addressing mode, supervisor expanded addressing
mode, and user expanded addressing mode. These three modes are described below.
(1) Kernel expanded addressing mode
When the Status register’s KX bit has been set, an expanded TLB miss exception vector is used when a TLB
miss occurs for the kernel address. While in kernel mode, the MIPS III operation code can always be used,
regardless of the KX bit.
(2) Supervisor expanded addressing mode
When the Status register’s SX bit has been set, the MIPS III operation code can be used when in supervisor
mode and an expanded TLB miss exception vector is used when a TLB miss occurs for the supervisor address.
(3) User expanded addressing mode
When the Status register’s UX bit has been set, the MIPS III operation code can be used when in user mode, and
an expanded TLB miss exception vector is used when a TLB miss occurs for the user address. When this bit is
cleared, the MIPS I and II operation codes can be used, as can 32-bit virtual addresses.
2.6.3.3 Reverse endian
When the Status register’s RE bit has been set, the endian ordering is reversed to adopt the user software’s
perspective. However, the RE bit of the Status register must be set to 0 since the VR4120A supports the little-endian
order only.
2.6.3.4 Bootstrap exception vector (BEV)
The BEV bit is used to generate an exception during operation testing (diagnostic testing) of the cache and main
memory system. This bit is automatically set to 1 after reset or NMI exception.
When the Status register’s BEV bit has been set, the address of the TLB miss exception vector is changed to the
virtual address FFFF_FFFF_BFC0_0200H and the ordinary execution vector is changed to address
FFFF_FFFF_BFC0_0380H.
When the BEV bit is cleared, the TLB miss exception vector’s address is changed to FFFF_FFFF_8000_0000H
and the ordinary execution vector is changed to address FFFF_FFFF_8000_0180H.
2.6.3.5 Cache error check
The Status register’s CE bit has no meaning because the VR4120A does not support cash parity.
2.6.3.6 Parity error prohibit
When the Status register’s DE bit has been set, the processor does not issue any cache parity error exceptions.
2.6.3.7 Interrupt enable (IE)
When the Status register’s IE bit has been cleared, no interrupts can be received except for reset interrupts and
nonmaskable interrupts.