CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 63
2.1.5 Coprocessors (CP0)
MIPS ISA defines 4 types of coprocessors (CP0 to CP3).
•CP0 translates virtual addresses to physical addresses, switches the operating mode (kernel, supervisor, or
user mode), and manages exceptions. It also controls the cache subsystem to analyze a cause and to return
from the error state.
•CP1 is reserved for floating-point instructions.
•CP2 is reserved for future definition by MIPS.
•CP3 is no longer defined. CP3 instructions are reserved for future extensions.
Figure 2-7 shows the definitions of the CP0 register, and Table 2-1 shows simple descriptions of each register. For
the detailed descriptions of the registers related to the virtual system memory, refer to Section 2.4 Memory
Management System. For the detailed descriptions of the registers related to exception handling, refer to Section
2.5 Exception Processing.
Figure 2-7. CP0 Registers
0
Notes 1. for Memory management
2. for Exception handling
Remark RFU: Reserved for future use
Register No. Register name
IndexNote 1
1RandomNote 1
2EntryLo0Note 1
3EntryLo1Note 1
4ContextNote 2
5PageMaskNote 1
6WiredNote 1
7RFU
8BadVAddrNote 1
9CountNote 2
10 EntryHiNote 1
11 CompareNote 2
12 StatusNote 2
13 CauseNote 2
14 EPCNote 2
15 PRIdNote 1
16
Register No. Register name
ConfigNote 1
17 LLAddrNote 1
18 WatchLoNote 2
19 WatchHiNote 2
20 XContextNote 2
21 RFU
22 RFU
23 RFU
24 RFU
25 RFU
26 PErrNote 2
27 CacheErrNote 2
28 TagLoNote 1
29 TagHiNote 1
30 ErrorEPCNote 2
31 RFU