CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 135
Figure 2-52. Status Register Diagnostic Status Field
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0BEV TS SR 0CH CE DE
11111112
BEV : Specifies the base address of a TLB Refill exception vector and common exception vector (0 →
Normal, 1 → Bootstrap).
TS : Occurs the TLB to be shut down (read-only) (0 → Not shut down, 1 → Shut down). This bit is used to
avoid any problems that may occur when multiple TLB entries match the same virtual address. After
the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut down
even if a TLB entry matching a virtual address is marked as being invalid (with the V bit cleared).
SR : Occurs a Soft Reset or NMI exception (0 → Not occurred, 1 → Occurred).
CH : CP0 condition bit (0 → False, 1 → True). This bit can be read and written by software only; it cannot
be accessed by hardware.
CE, DE: These are prepared to maintain compatibility with the VR4100, and are not used in the VR4120A Core
hardware.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
The status register has the following fields where the modes and access status are set.
(1) Interrupt enable
Interrupts are enabled when all of the following conditions are true:
IE is set to 1.
EXL is cleared to 0.
ERL is cleared to 0.
The appropriate bit of the IM is set to 1.
(2) Operating modes
The following Status register bit settings are required for User, Kernel, and Supervisor modes.
The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0.
The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0.
The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1.
(3) 32- and 64-bit modes
The following Status register bit settings select 32- or 64-bit operation for User, Kernel, and Supervisor operating
modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-
bit operation for User, Kernel and Supervisor modes can be set independently.
64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel
mode.
64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1.
64-bit addressing and operations are enabled for User mode when UX bit = 1.
(4) Kernel address space accesses
Access to the kernel address space is allowed when the processor is in Kernel mode.
(5) Supervisor address space accesses
Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode.
(6) User address space accesses
Access to the user address space is allowed in any of the three operating modes.