APPENDIX A MIPS III INSTRUCTION SET DETAILS
514 Preliminary Users Manual S15543EJ1V0UM
LW Load Word LW
base

LW

1 0 0 0 1 1 rt offset

31 26 25 21 20 16 15 0
655 16
Format:
LW rt, offset (base)
Description:
The 16-bit
offset
is sign-extended and added to the contents of general register
base
to form a virtual address.
The contents of the word at the memory location specified by the effective address are loaded into general register
rt
. In 64-bit mode, the loaded word is sign-extended.
If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.
Operation:
32 T: vAddr ((offset15)16 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddrpAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 02))
mem LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte vAddr2...0 xor (BigEndianCPU || 02)
GPR [rt] mem31 + 8 * byte...8 * byte
64 T: vAddr ((offset15)48 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddr pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 02))
mem LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte vAddr2...0 xor (BigEndianCPU || 02)
GPR
[
rt
]
(
mem31 + 8 * byte
)
32 || mem31 + 8 * byte...8 * byte
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception