CHAPTER 2 VR4120A
156 Preliminary User’s Manual S15543EJ1V0UM
2.5.4.14 Trap exception
(1) Cause
The Trap exception occurs when a TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, TLTI, TLTUI, TEQI, or
TNEI instruction results in a TRUE condition. This exception is not maskable.
(2) Processing
The common exception vector is used for this exception, and the Tr code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the trap instruction causing the exception unless the instruction is in a
branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the
BD bit of the Cause register is set to 1.
(3) Servicing
At the time of a Trap exception, the kernel reports the UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point
exception/integer overflow) signal to the current process, but the exception is usually fatal.
2.5.4.15 Integer overflow exception
(1) Cause
An Integer Overflow exception occurs when an ADD, ADDI, SUB, DADD, DADDI, or DSUB instruction results in a
2’s complement overflow. This exception is not maskable.
(2) Processing
The common exception vector is used for this exception, and the Ov code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the instruction that caused the exception unless the instruction is in a
branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the
BD bit of the Cause register is set to 1.
(3) Servicing
At the time of the exception, the kernel reports the UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point
exception/integer overflow) signal to the current process, and this exception is usually fatal.