NEC uPD98502 - page 399

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 399
7.5.15 P_BCNT (Bridge Control Register)
This register is used to control the PCI-internal bus bridge function.
R/WBits Field
Internal
bus
PCI
Default Description
31 INITD R/W R 0 Initialize done.
The VR4120A should set this bit to ‘1’ after the initialization of the
chip.
The PCI Controller always issues “retry” against the access on
PCI to the PCI Controller bus when this bit is set to a ‘0’.
30:6 Reserved - - 0 Hardwired to ‘0’s.
5 ICMDS R/W R/W 0 Internal bus Command Select.
When this bit is set to ‘1’, the PCI Controller uses Memory
command on Internal bus.
When this bit is set to ‘0’, the PCI Controller uses I/O command
on Internal bus.
4 DACEN R/W R/W 0 Dual Address Cycle Enable.
Reserved for the future use. The bit has to be set to 0.
3 PDRTD R/W R/W 0 PCI Delayed Read Transaction Disable.
‘1’ disables the PCI Controller to generate Delayed Read
Transaction on PCI bus.
PCI Read transactions are executed as None Delayed Read
Transaction.
2 PPWRD R/W R/W 0 PCI Posted Write Transaction Disable.
‘1’ disables the PCI Controller to generate Posted Write
Transaction on PCI bus.
PCI Write transactions are executed as None Posted Write
Transaction.
1 IDRTD R/W R/W 0 Internal bus Delayed Read Transaction Disable.
‘1’ disables the PCI Controller to generate Delayed Read
Transaction on Internal bus.
PCI Read transactions are executed as None Delayed Read
Transaction.
0 IPWRD R/W R/W 0 Internal bus Posted Write Transaction Disable.
‘1’ disables the PCI Controller to generate Posted Write
Transaction on Internal bus.
PCI Write transactions are executed as None Posted Write
Transaction.