APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary Users Manual S15543EJ1V0UM 489
DSRA32 Doubleword Shift Right Arithmetic + 32 DSRA32
0
0 0 0 0 0
SPECIAL

0 0 0 0 0 0 rt rd sa DSRA32

1 1 1 1 1 1

31 26 25 21 20 16 15 11 10 6 5 0
6 5555 6
Format:
DSRA32 rd, rt, sa
Description:
The contents of general register
rt
are shifted right by
32
+
sa
bits, sign-extending the high-order bits. The result is
placed in register
rd
.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
64 T: s 1 || sa
GPR [rd] (GPR [rt]63)s || GPR [rt]63..s
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)