8Preliminary User’s Manual S15543EJ1V0UM
2.1.6 Floating-point unit (FPU)................................................................................................................64
2.1.7 CPU core memory management system (MMU)...........................................................................65
2.1.8 Translation lookaside buffer (TLB).................................................................................................65
2.1.9 Operating modes...........................................................................................................................65
2.1.10 Cache............................................................................................................................................65
2.1.11 Instruction pipeline.........................................................................................................................66
2.2 MIPS III Instruction Set Summary.............................................................................................662.2.1 MIPS III ISA instruction formats.....................................................................................................66
2.2.2 Instruction classes.........................................................................................................................67
2.3 Pipeline........................................................................................................................................842.3.1 Pipeline stages..............................................................................................................................84
2.3.2 Branch delay..................................................................................................................................87
2.3.3 Load delay.....................................................................................................................................87
2.3.4 Pipeline operation..........................................................................................................................88
2.3.5 Interlock and exception handling...................................................................................................94
2.3.6 Program compatibility..................................................................................................................100
2.4 Memory Management System ................................................................................................1012.1.1 Translation lookaside buffer (TLB)..............................................................................................101
2.1.2 Virtual address space..................................................................................................................102
2.1.3 Physical address space...............................................................................................................116
2.1.4 System control coprocessor.........................................................................................................117
2.1.5 CP0 registers...............................................................................................................................119
2.5 Exception Processing.............................................................................................................1292.5.1 Exception processing operation...................................................................................................129
2.5.2 Precision of exceptions................................................................................................................130
2.5.3 Exception processing registers....................................................................................................130
2.1.4 Details of exceptions....................................................................................................................142
2.1.5 Exception processing and servicing flowcharts............................................................................158
2.2 Initialization Interface..............................................................................................................1652.2.1 Cold reset....................................................................................................................................165
2.2.2 Soft reset.....................................................................................................................................165
2.2.3 VR4120A processor modes..........................................................................................................165
2.3 Cache Memory..........................................................................................................................1682.3.1 Memory organization...................................................................................................................168
2.3.2 Cache organization......................................................................................................................169
2.3.3 Cache operations.........................................................................................................................171
2.3.4 Cache states................................................................................................................................172
2.3.5 Cache state transition diagrams..................................................................................................173
2.3.6 Cache data integrity.....................................................................................................................174
2.3.7 Manipulation of the caches by an external agent.........................................................................181
2.4 CPU Core Interrupts.................................................................................................................1822.4.1 Non-maskable interrupt (NMI)......................................................................................................182
2.4.2 Ordinary interrupts.......................................................................................................................182
2.4.3 Software interrupts generated in CPU core.................................................................................182
2.4.4 Timer interrupt.............................................................................................................................182
2.4.5 Asserting interrupts......................................................................................................................183