APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary Users Manual S15543EJ1V0UM 511
LH Load Halfword LH
base

LH

1 0 0 0 0 1 rt offset

31 26 25 21 20 16 15 0
655 16
Format:
LH rt, offset (base)
Description:
The 16-bit
offset
is sign-extended and added to the contents of general register
base
to form a virtual address.
The contents of the halfword at the memory location specified by the effective address are sign-extended and
loaded into general register
rt
.
If the least-significant bit of the effective address is non-zero, an address error exception occurs.
Operation:
32 T: vAddr ((offset15)16 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddr pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian2 || 0))
mem LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte vAddr2...0 xor (BigEndianCPU2 || 0)
GPR [rt] (mem15 + 8 * byte)16 || mem15 + 8 * byte...8 * byte
64 T: vAddr ((offset15)48 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddr pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian2 || 0))
mem LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte vAddr2...0 xor (BigEndianCPU2 || 0)
GPR [rt]
(
mem15 + 8 * byte
)
48 || mem15 + 8 * byte...8 * byte
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception