APPENDIX A MIPS III INSTRUCTION SET DETAILS
566 Preliminary Users Manual S15543EJ1V0UM
SWR Store Word Right (2/3) SWR
Operation:
32 T: vAddr ((offset15)16 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddrpAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian3)
if BigEndianMem = 1 then
pAddr pAddrPSIZE - 1...2 || 02
endif
byte vAddr1...0 xor BigEndianCPU2
if (vAddr2 xor BigEndianCPU) = 0 then
data 032 || GPR [rt]31 8 * byte...0 || 08 * byte
else
data GPR [rt]31 8 * byte || 08 * byte || 032
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
64 T: vAddr ((offset15)48 || offset15...0) + GPR [base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddr pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian3)
if BigEndianMem = 1 then
pAddr pAddrPSIZE - 1...2 || 02
endif
byte vAddr1...0 xor BigEndianCPU2
if (vAddr2 xor BigEndianCPU) = 0 then
else
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
data 032 || GPR [rt]31 8 * byte...0 || 08 * byte
data GPR [rt]31 8 * byte || 08 * byte || 032