NEC uPD98502 - page 94

CHAPTER 2 VR4120A
94 Preliminary User’s Manual S15543EJ1V0UM
2.3.5 Interlock and exception handling
Smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are
detected. Interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that
are handled using software are called exceptions. As shown in Figure 2-19, all interlock and exception conditions are
collectively referred to as faults.
Figure 2-19. Relationship among Interlocks, Exceptions, and Faults
SlipStallAbort
Exceptions Interlocks
Software Hardware
Faults
At each cycle, exception and interlock conditions are checked for all active instructions.
Because each exception or interlock condition corresponds to a particular pipeline stage, a condition can be traced
back to the particular instruction in the exception/interlock stage, as shown in Table 2-23. For instance, an LDI
Interlock is raised in the Register Fetch (RF) stage.
Tables 2-24 and 2-25 describe the pipeline interlocks and exceptions listed in Table 2-23.
Table 2-23. Correspondence of Pipeline Stage to Interlock and Exception Conditions
Status
Stage IF RF
(IT)
EX DC WB
Stall −ITM
ICM
−DTM
DCM
DCB
−Interlock
Slip −LDI
MDI
SLI
CP0
−−−
Exception IAErr NMI
ITLB
IPErr
INTr
IBE
SYSC
BP
CUn
RSVD
Trap
OVF
DAErr
Reset
DTLB
TMod
DPErr
WAT
DBE
−
Remark In the above table, exception conditions are listed up in higher priority order.