14 Preliminary User’s Manual S15543EJ1V0UM
CHAPTER 7 PCI CONTROLLER.........................................................................................................370
7.1 Overview................................................................................................................................... 370
7.2 Bus Bridge Functions..............................................................................................................371
7.2.1 Internal bus to PCI transaction.....................................................................................................371
7.2.2 PCI to internal bus transaction .....................................................................................................376
7.2.3 Abnormal Termination..................................................................................................................381
7.2.4 Warning for Deadlocks.................................................................................................................382
7.3 PCI Power Management Interface..........................................................................................383
7.3.1 Power state..................................................................................................................................383
7.3.2 Power management event ...........................................................................................................383
7.3.3 Power supply...............................................................................................................................383
7.3.4 Power state transition ..................................................................................................................384
7.4 Functions in Host-mode..........................................................................................................386
7.4.1 Generating configuration cycle....................................................................................................386
7.4.2 PCI bus arbiter.............................................................................................................................388
7.4.3 Reset output................................................................................................................................389
7.4.4 Interrupt input...............................................................................................................................389
7.5 Registers...................................................................................................................................390
7.5.1 Register map...............................................................................................................................390
7.5.2 P_PLBA (PCI Lower Base Address Register)..............................................................................391
7.5.3 P_IBBA (Internal Bus Base Address Register) ............................................................................391
7.5.4 P_VERR (Version Register).........................................................................................................391
7.5.5 P_PCAR (PCI Configuration Address Register) ..........................................................................392
7.5.6 P_PCDR (PCI Configuration Data Register) ................................................................................392
7.5.7 P_IGSR (Internal Bus-side General Status Register) ..................................................................393
7.5.8 P_IIMR (Internal Bus Interrupt Mask Register) ............................................................................394
7.5.9 P_PGSR (PCI-side General Status Register) ..............................................................................395
7.5.10 P_IIMR (Internal Bus Interrupt Mask Register)............................................................................396
7.5.11 P_PIMR (PCI Interrupt Mask Register)........................................................................................397
7.5.12 P_HMCR (Host Mode Control Register)......................................................................................398
7.5.13 P_PCDR (Power Consumption Data Register)............................................................................398
7.5.14 P_PDDR (Power Dissipation Data Register)...............................................................................398
7.5.15 P_BCNT (Bridge Control Register)..............................................................................................399
7.5.16 P_PPCR (PCI Power Control Register).......................................................................................400
7.5.17 P_SWRR (Software Reset Register)...........................................................................................400
7.5.18 P_RTMR (Retry Timer Register)..................................................................................................401
7.5.19 P_CONFIG (PCI Configuration Registers)...................................................................................401
7.2 Information for Software .........................................................................................................411
7.2.1 NIC mode.....................................................................................................................................411
7.2.2 Host mode...................................................................................................................................412
CHAPTER 8 UART...............................................................................................................................414
8.1 Overview................................................................................................................... ................414
8.2 UART Block Diagram ...............................................................................................................414
8.3 Registers...................................................................................................................................415
8.3.1 Register map...............................................................................................................................415
8.3.2 UARTRBR (UART Receiver data Buffer Register).......................................................................416
8.3.3 UARTTHR (UART Transmitter data Holding Register) ................................................................416