NEC uPD98502 18 , LIST OF FIGURES (3/5)

18 Preliminary User’s Manual S15543EJ1V0UM
LIST OF FIGURES (3/5)
Figure No. Title Page
2-71 Instruction Cache State Diagram.................................................................................................................173
2-72 Data Check Flow on Instruction Fetch.........................................................................................................174
2-73 Data Check Flow on Load Operations.........................................................................................................174
2-74 Data Check Flow on Store Operations.........................................................................................................175
2-75 Data Check Flow on Index_Invalidate Operations.......................................................................................175
2-76 Data Check Flow on Index_Writeback_Invalidate Operations.....................................................................176
2-77 Data Check Flow on Index_Load_Tag Operations......................................................................................176
2-78 Data Check Flow on Index_Store_Tag Operations......................................................................................177
2-79 Data Check Flow on Create_Dirty Operations.............................................................................................177
2-80 Data Check Flow on Hit_Invalidate Operations............................................................................................178
2-81 Data Check Flow on Hit_Writeback_Invalidate Operations..........................................................................178
2-82 Data Check Flow on Fill Operations.............................................................................................................179
2-83 Data Check Flow on Hit_Writeback Operations...........................................................................................179
2-84 Writeback Flow............................................................................................................................................180
2-85 Refill Flow....................................................................................................................................................180
2-86 Writeback & Refill Flow................................................................................................................................181
2-87 Non-maskable Interrupt Signal.....................................................................................................................182
2-88 Hardware Interrupt Signals..........................................................................................................................183
2-89 Masking of Interrupt Request Signals..........................................................................................................184
3-1 Bit and Byte Order of Endian Modes............................................................................................................227
3-2 Half-word Data Array Example.....................................................................................................................227
3-3 Word Data Array Example...........................................................................................................................228
4-1 Block Diagram of ATM Cell Processor.........................................................................................................230
4-2 AAL-5 Sublayer and ATM Layer..................................................................................................................232
4-3 AAL-5 Sublayer and ATM Layer..................................................................................................................233
4-4 ATM Cell......................................................................................................................................................234
4-5 LLC Encapsulation.......................................................................................................................................235
4-6 Memory Space from VR4120A and RISC Core............................................................................................236
4-7 Work RAM and Register Space...................................................................................................................237
4-8 Tx Packet.....................................................................................................................................................247
4-9 Tx Buffer Elements......................................................................................................................................248
4-10 Tx Packet Descriptor....................................................................................................................................249
4-11 Tx Buffer Descriptor/Link Pointer.................................................................................................................250
4-12 Rx Pool Structure.........................................................................................................................................251
4-13 Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer..............................................252
4-14 Rx Pool Descriptor.......................................................................................................................................253
4-15 Rx Buffer Descriptor/ Link Pointer................................................................................................................254
4-16 Transfer of F/W............................................................................................................................................255
4-17 Instruction RAM and Instruction Cache........................................................................................................256
4-18 Set_Link_Rate Command............................................................................................................................258