Preliminary User’s Manual S15543EJ1V0UM 15
8.3.4 UARTIER (UART Interrupt Enable Register)...............................................................................416
8.3.5 UARTDLL (UART Divisor Latch LSB Register)...........................................................................416
8.3.6 UARTDLM (UART Divisor Latch MSB Register)......................................................................... 417
8.3.7 UARTIIR (UART Interrupt ID Register)........................................................................................418
8.3.8 UARTFCR (UART FIFO Control Register)..................................................................................419
8.3.9 UARTLCR (UART Line Control Register)....................................................................................420
8.3.10 UARTMCR (UART Modem Control Register)..............................................................................421
8.3.11 UARTLSR (UART Line Status Register)......................................................................................422
8.3.12 UARTMSR (UART Modem Status Register)...............................................................................423
8.3.13 UARTSCR (UART Scratch Register)...........................................................................................423
CHAPTER 9 TIMER..............................................................................................................................424
9.1 Overview................................................................................................................................... 424
9.2 Block Diagram..........................................................................................................................424
9.3 Registers...................................................................................................................................425
9.3.1 Register map...............................................................................................................................425
9.3.2 TMMR (Timer Mode Register).....................................................................................................425
9.3.3 TM0CSR (Timer CH0 Count Set Register)..................................................................................426
9.3.4 TM1CSR (Timer CH1 Count Set Register)..................................................................................426
9.3.5 TM0CCR (Timer CH0 Current Count Register)...........................................................................426
9.3.6 TM1CCR (Timer CH1 Current Count Register)...........................................................................426
CHAPTER 10 MICRO WIRE .................................................................................................................427
10.1 Overview................................................................................................................................... 427
10.2 Operations................................................................................................................................ 428
10.2.1 Data read at the power up load ...................................................................................................428
10.2.2 Accessing to EEPROM................................................................................................................428
10.3 Registers...................................................................................................................................429
10.3.1 Register map ...............................................................................................................................429
10.3.2 ECCR (EEPROM Command Control Register)...........................................................................429
10.3.3 ERDR (EEPROM Read Data Register).......................................................................................429
10.3.4 MACAR1 (MAC Address Register 1)...........................................................................................429
10.3.5 MACAR2 (MAC Address Register 2)...........................................................................................429
10.3.6 MACAR3 (MAC Address Register 3)...........................................................................................430
APPENDIX A MIPS III INSTRUCTION SET D ETAILS......................................................................431
A.1 Instruction Notation Conventions........................................................................................431
A.2 Load and Store Instructions................................................................................................ 433
A.3 Jump and Branch Instructions............................................................................................ 434
A.4 System Control Coprocessor (CP0) Instructions............................................................. 435
A.5 CPU Instruction....................................................................................................................... 435
A.6 CPU Instruction Opcode Bit Encoding.............................................................................. 588
APPENDIX B VR4120A COPROCESSOR 0 HAZ ARDS....................................................................590