APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary Users Manual S15543EJ1V0UM 461
BLTZL Branch On Less Than Zero Likely BLTZL
rs
REGIMM
0 0 0 0 0 1

BLTZL

0 0 0 1 0 offset

31 26 25 21 20 1615 0
655 16
Format:
BLTZ rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. If the contents of general register
rs
are smaller than zero when
compared to zero, then the program branches to the target address, with a delay of one instruction. If the
conditional branch is not taken, the instruction in the branch delay slot is nullified.
Operation:
32 T: target (offset15)14 || offset || 02
condition (GPR [rs]31 = 1)
T+1: if condition then
PC PC + target
else
NullifyCurrentInstruction
endif
64 T: target (offset15)46 || offset || 02
condition (GPR [rs]63 = 1)
T+1: if condition then
PC PC + target
else
NullifyCurrentInstruction
endif
Exceptions:
None