CHAPTER 4 ATM CELL PROCESSOR
232 Preliminary User’s Manual S15543EJ1V0UM
4.1.2.4 Other blocks
Work-RAM is 12 K-byte memory. Tables and Pool Descriptors are located in this RAM. It is shared between MCU
and UTOPIA Bus Controller block. It also can be accessed by VR4120A RISC Processor, using Indirect-Access.
4.1.3 ATM cell processing operation overview
In this section, only overview is described. Please refer to section 4.7 for more detailed information.
ATM Cell Processor supports AAL-5 SAR sublayer and ATM layer functions. This block provides LLC
encapsulation.
Figure 4-2. AAL-5 Sublayer and ATM Layer
CPCS PDU recovery
- CPCS-UU field notification
- CPI field notification
- packet length check & notification
- CRC check
CPCS PDU construction
CPCS PDU generation
- padding addition
- CPCS-UU field addition
- CPI field addition
- packet length calcuration & insertion
- CRC-32 calcuration & insertion
Dividing a pacekt into cells
Cell processing & demultiplexing
- congestion indication
- cell payload type identification
Cell processing & multiplexing
- cell scheduling
- cell header addition
UTOPIA
AAL-5
SAR Sublayer
ATM layer
VR4120A RISC Processor