NEC uPD98502 SDRAM Space 64 K

CHAPTER 4 ATM CELL PROCESSOR
236 Preliminary User’s Manual S15543EJ1V0UM
4.2 Memory Space
Although the RISC Core in the ATM Cell Processor is a 32-bit MPU, its physical memory space is 24-bit width.
Figure 4-6. Memory Space from VR4120A and RISC Core
Work RAM &
Register Space
Instruction
space
A_IBBAR:IBus data Base Address Register
A_INBAR:Instruction Base Address Register
Shared
Memory
(4 MB ma x.)
40_0000H+
(Content of A_IBBAR)
7F_FFFFH+
(Content of A_IBBAR)
(Content of A_INBAR)
0F_FFFFH+
(Content of A_INBAR)
SDRAM Space 64 K
Instruction
space
Shared
Memory
(4 MB ma x.)
xx00_0000H
xx0F_FFFFH
xx40_0000H
xx80_0000H
xx80_FFFFH
xxFF_FFFFH
xxFF_F000H
Peripheral
xxFF_E3FFH
xxFF_E000H
Internal Data
RAM (1 KB)
RISC Core
Memory Space
1001_FFFFH
1001_0000H
VR4120A RISC Processor
Memory Space
Work RAM &
Register Space
The configuration is shown as Figure 4-6. It contains instruction space, shared memory space, work RAM, internal
memory space, and peripheral space.
VR4120A and RISC Core in the ATM Cell Processor share an external memory space. Shared memory will be
implemented by using SDRAM devices. The address in VR4120A memory space will be determined by S/W and
notified to RISC Core by setting A_IBBAR (IBUS data Base Address Register). Its capacity depends on the total
capacity of physical memory, but not exceeds 4 MB.