16 Preliminary User’s Manual S15543EJ1V0UM
LIST OF FIGURES (1/5)Figure No. Title Page
1-1 Examples of the
µ
PD98502 System Configuration........................................................................................24
1-2 Block Diagram of the
µ
PD98502....................................................................................................................25
1-3 Block Diagram of VR4120A RISC Processor..................................................................................................26
1-4 Block Diagram of IBUS..................................................................................................................................27
1-5 Block Diagram of System Controller..............................................................................................................28
1-6 Block Diagram of ATM Cell Processor...........................................................................................................29
1-7 Block Diagram of Ethernet Controller.............................................................................................................30
1-8 Block Diagram of USB Controller...................................................................................................................31
1-9 Block Diagram of PCI Bus controller..............................................................................................................32
1-10 Memory Map..................................................................................................................................................53
1-11 Reset Configuration.......................................................................................................................................54
1-12 Interrupt Signal Connection............................................................................................................................55
1-13 Block Diagram of Clock Control Unit..............................................................................................................56
2-1 VR4120A Core Internal Block Diagram...........................................................................................................57
2-2 VR4120A Registers........................................................................................................................................59
2-3 CPU Instruction Formats (32-bit Length Instruction)......................................................................................60
2-4 Little-Endian Byte Ordering in Word Data......................................................................................................61
2-5 Little-Endian Byte Ordering in Double Word Data..........................................................................................61
2-6 Misaligned Word Accessing (Little-Endian)....................................................................................................62
2-7 CP0 Registers................................................................................................................................................63
2-8 MIPS III ISA CPU Instruction Formats...........................................................................................................66
2-9 Pipeline Stages (MIPS III Instruction Mode)...................................................................................................84
2-10 Instruction Execution in the Pipeline..............................................................................................................85
2-11 Pipeline Activities (MIPS III)...........................................................................................................................85
2-12 Branch Delay (In MIPS III Instruction Mode)..................................................................................................87
2-13 ADD Instruction Pipeline Activities (In MIPS III Instruction Mode)..................................................................88
2-14 JALR Instruction Pipeline Activities (In MIPS III Instruction Mode)................................................................89
2-15 BEQ Instruction Pipeline Activities (In MIPS III Instruction Mode)..................................................................90
2-16 TLT Instruction Pipeline Activities..................................................................................................................91
2-17 LW Instruction Pipeline Activities (In MIPS III Instruction Mode)....................................................................92
2-18 SW Instruction Pipeline Activities (In MIPS III Instruction Mode)...................................................................93
2-19 Relationship among Interlocks, Exceptions, and Faults.................................................................................94
2-20 Exception Detection.......................................................................................................................................96
2-21 Data Cache Miss Stall....................................................................................................................................97
2-22 CACHE Instruction Stall.................................................................................................................................97
2-23 Load Data Interlock........................................................................................................................................98
2-24 MD Busy Interlock..........................................................................................................................................99
2-25 Virtual-to-Physical Address Translation.......................................................................................................102
2-26 32-bit Mode Virtual Address Translation......................................................................................................104
2-27 64-bit Mode Virtual Address Translation......................................................................................................105
2-28 User Mode Address Space..........................................................................................................................106