NEC uPD98502 3.5 IBUS Interface

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 221
3.5 IBUS Interface
3.5.1 Overview
• IBUS Master and target capability
• 64-word (256-byte) IBUS Slave TxFIFO (IBUS read data from IBUS)
• 64-word (256-byte) IBUS Slave RxFIFO (IBUS write data to IBUS)
• 4-word (16-byte) IBUS Master TxFIFO (VR4120A read data from IBUS)
• 4-word (16-byte) IBUS Master RxFIFO (VR4120A write data to IBUS)
• Supports bus timer to detect IBUS stall
• 66-MHz IBUS clock rate
• Support 266 MB/sec (32 bits @66 MHz) burst on IBUS
• Support endian conversion between SysAD BUS and IBUS master I/F
• Support endian conversion between memory BUS and IBUS slave I/F
3.5.2 Endian Conversion on IBUS master
“HSWP” bit on S_GMR is enabler for endian converter that is located on space between SysAD interface and IBUS
master interface, so this works only IBUS target area. This converter is effective at the case of address swap mode
only. This converter performs following data operations.
Table 3-11. Endian Translation Table for the data swap mode (IBUS master)
HSWP
on
GMR
Data Size offset
address
[1:0] Note
Before Translation
input data[31:0]
in Data Phase
After Translation
output data[31:0]
in Data Phase
Remark
0 any any [31:0] [31:0] i.e. now
1 Over 1 word 0
1 byte 0, 1, 2, 3 [31:24] [23:16] [15:8] [7:0] [7:0] [15:8] [23:16] [31:24] -
2 bytes 0, 2 [31:16] [15:0] [15:0] [31:16] -
3 bytes 0 [31:8] [7:0] [31:24] [23:0] -
1 [31:24] [23:0] [31:8] [7:0] -
Note This offset address[1:0] is expression on big endian mode.
In the following Figure, Upper side is 4 octet data of SysAD BUS. And Under side is 4 octet data of IBUS master
I/F.