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Intel
IQ80321 manual
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Contents
Main
Intel IQ80321 I/O Processor Evaluation Platform
Contents
Page
Page
Page
Page
Figures
Tables
Page
Revision History
Page
Introduction 1
1.1 Document Purpose and Scope
1.2 Related Documents
Introduction
1.3 Electronic Information
Tabl e 3 provides additional information on th e major components of IQ80321.
1.4 Component References
Table 2. Electronic Information
Table 3. Component Reference
1.5 Terms and Definit ions
1.6 Intel 80321 I/O Processor
Page
Introduction
1.7 Intel IQ80321 Evaluation Platform Board Features
Table 5. Summary of Features
Getting Started 2
2.1 Kit Content
2.2 Hardware Installation
2.2.1 First-Time Installation and Test
2.3 Factory Settings
2.4 Development Strategy
2.4.1 Supported Tool Buckets
2.4.2 Contents of the Flash
2.5 Target Monitors
2.5.1 Redhat Redboot
2.5.2 ARM Firmware Suite
Page
Getting Started
2.6 Host Communications Examples
Server/Desktop/Backplane
e
l
b
2.6.3 JTAG Debug Communication
Using a JTAG Emulator: Figure 4. JTAG Debug Communication
2.6.4 GNUPro GDB/Insight
Page
Page
2.6.5 ARM Extended Debugger
Page
Hardware Reference Section 3
3.1 Functional Diagram
Figure 5 shows the functional block for the IQ80321 . Figure 5. Functional Block Diagram
Intel IQ80321 I/O Processor Evaluation Platform
3.2 Board Form-Factor/Connectivity
DDR DIMM Connector
Battery
Intel
Figure 6. Board Form Factor
3.3 Power
3.4 Memory Subsystem
3.4.1 DDR SDRAM
3.4.1.1 Battery Backup
3.4.2 Flash Memory Requirements
Page
3.6 Interrupt Routing
3.7 Intel IQ80321 Evaluation Platform Board Peripheral Bus
The IQ80321 populates the per ipheral bus as depicted by F igure8.
The devices on the bus include Flash ROM, UART, HEX display, and rotary switch.
Figure 8. Intel IQ80321 Evaluation Platform Board Peripheral Bus Topology
Table 11. Peripheral Bus Features
3.7.1 Flash ROM
Table 12. Flash ROM Features
Figure 9. Flash Connection on Periphera l Bus
3.7.2 UART
Table 13. UART Features
Figure 10. UART Connection on the Peripheral Bus
3.7.3 H EX Display
Table 14. HEX Display on the Perip heral Bus
Figure 11. HEX Display Connection on the Peripheral Bus
3.7.4 Rotary Switch
3.7.5 Battery Status
Table 16. Battery Status Buffer Requirements
Figure 13. Battery Status Buffer on Peripheral Bus
3.8 Debug Interface
3.8.1 Console Serial Port
3.8.2 Ethernet Port
3.8.2.1 Intel 82544EI Gigabit Ethernet Controller
3.8.3 JTAG Debug
3.8.3.1 JTAG Port
3.8.4 Logic-Analyzer Connectors
3.8.5 Mictor J3F2
3.8.6 Mictor J2F1
3.8.7 Mictor J1C1
3.8.8 Mictor J3C1
3.8.9 Mictor J2C1
3.9 Board Reset Scheme
TRST Pin
Figure 15. RESET Sources
Reset from Primary PCI-X Connector
To PCI-X Bridge Reset
3.10 Switches and Jumpers
3.10.1 Switch Summary
Table 24. Switch Summary
3.10.2 PCIX Initialization Summary
3.10.2.1 User Defined Switches
PCI-X 100/133 PCI-X 66
3.10.2.2 PCI-X Bridge Initialization Signals
3.10.3 Default Switch Settings - Visual
Table 25. Switch S7E1
Table 26. Switch S8E1
Table 27. Switch S8E2
Table 28. Switch S9E1
3.10.4 Jumper Summary
3.10.5 Connector Summary
3.10.6 General Purpose Input/Output Header
3.10.7 Secondary PCI/PCI-X Operation Settings
3.10.8 Primary PCI/PCI-X Operation Settings
Table 34. Secondary PCI/PCI-X Operation Settings
Table 35. Primary PCI/PCI-X Operation Settings
3.10.9 Detail Descriptions of Switches/Jumpers
3.10.9.1 Switch S7E1- 2/3
3.10.9.2 Switch S7E1- 4/5
3.10.9.3 Switch S7E1- 6/7
3.10.9.4 Switch S7E1- 8
3.10.9.5 Switch S8E1- 2
3.10.9.6 Switch S8E1- 3
3.10.9.7 Switch S8E1- 4
3.10.9.8 Switch S8E1- 5
3.10.9.9 Switch S8E1- 6
3.10.9.10 Switch S8E1- 7
3.10.9.11 Switch S8E1- 8
3.10.9.12 Switch S8E2 - 1/2
3.10.9.13 Switch S8E2 - 4
3.10.9.14 Switch S9E1 - 1:3
3.10.9.15 Switch S9E1 - 4
3.10.9.16 Switch S1D1 - 1/2
3.10.9.17 Switch S4D1 - 1/2
3.10.9.18 Switch S4D1 - 3/4
3.10.9.19 Jumper J1G2
3.10.9.20 Jumper J3E1
3.10.9.21 Jumper J3G1
3.10.9.22 Jumper J9E1
3.10.9.23 Jumper J9F1
Page
External RAID Section 4
4.1 Private Device Configuration
Figure 17. IDSEL Routing for Private Device Configuration
External RAID Section
4.2 Interrupt Routing
Figure 18. Interrupt Routing for Private Device Configuration
Intel 80321 I/O Processor
Software Reference 5
5.1 DRAM
5.2 Components on the Peripheral Bus
5.2.1 Flash ROM
5.2.2 UART
5.2.3 Rotary Switch
5.2.4 HEX Display
Page
5.3 Ethernet
Software Reference
5.4 Board Support Package (BSP) Examples
5.4.1 Intel 80321 I/O Processor Memory Map
Software Reference
5.4.2 Redboot* Intel IQ80321 Memory Map
The virtual memory maps use a C, B, and X column to indicate the caching policy for the region.
5.4.3 Redboot Intel IQ80321 Physical Memory Map - Visual
5.4.4 Redboot Intel IQ80321 Virtual Memory Map - Visual
5.4.5 Redboot Intel IQ80321 Files
5.4.6 Redboot Intel IQ80321 DDR Memory Initialization Sequence
5.4.7 Redboot Switching
Page
IQ80310 and IQ80321 Comparisons A
Page
Getting Started and Debugger B
B.1 Introduction
B.1.1 Purpose
B.1.2 Necessary Hardware and Software
B.1.3 Related Documents
B.1.4 Related Web Sites
B.2 Setup
B.2.1 Hardware Setup
B.2.2 Software Setup
B.3 New Project Setup
B.3.1 Creating a New Project
B.3.2 Configuration
B.4 Flashing with JTAG
B.4.1 Overview
B.4.2 Using Flash Programmer
B.5 Debugging Out of Flash
B.6 Building an Executable File From Example Code
B.7 Running the Code|Lab Debugger
B.7.1 Launching and Configuring Debugger
B.7.2 Manually Loading and Executing an Application Program
B.7.3 Displaying Source Code
B.7.4 Using Breakpoints
B.7.5 Stepping Through the Code
B.7.6 Setting Code|Lab Debug Options
B.8 Exploring the Code|Lab Debug Windows
B.8.1 Toolbar Icons
B.8.2 Workspace Window
B.8.3 Source Code
B.8.4 Debug and Console Windows
B.8.6 Registers Window
B.8.7 Watch Window
B.8.8 Variables Window
B.9 Debugging Basics
B.9.1 Overview
B.9.2 Hardware and Software Breakpoints
B.9.2.1 Software Breakpoints
B.9.2.2 Hardware Breakpoints
B.9.3 Exceptions/Trapping
Page
Getting Started and Debugger C
C.1 Introduction
C.1.1 Purpose
C.1.2 Necessary Hardware and Software
C.1.3 Related Documents
C.1.4 Related Web Sites
C.2 Setup
C.2.1 Hardware Setup
C.2.2 Software Setup
C.3 New Project Setup
C.3.1 Creating a New Project
C.3.2 Configuration
File Project code|lab EDE Tools Help Edit View Build, Debug
C.4 Flashing with JTAG
C.4.1 Overview
C.4.2 Using Flash Programmer
C.5 Debugging Out of Flash
C.6 Building an Executable File From Example Code
C.7 Running the Code|Lab Debugger
C.7.1 Launching and Configuring Debugger
C.7.2 Manually Loading and Executing an Appli cation Program
C.7.3 Displaying Source Code
C.7.4 Using Breakpoints
C.7.5 Stepping Through the Code
C.7.6 Setting Code|Lab Debug Options
C.8 Exploring the Code|Lab Debug Windows
C.8.1 Toolbar Icons
C.8.2 Workspace Window
C.8.3 Source Code
C.8.4 4 Debug and Console Windows
C.8.6 Registers Window
C.8.7 Watch Window
C.8.8 Variables Window
C.9 Debugging Basics
C.9.1 Overview
C.9.2 Hardware and Software Breakpoints
C.9.2.1 Software Breakpoints
C.9.2.2 Hardware Breakpoints
C.9.3 C.9.3 Exceptions/Trapping