Flash Memory Requirements | Intel IQ80321 manual

Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.4.2Flash Memory Requirements

Total Flash memory size is 8 MB.

Table 10. Flash Memory Requirements

Description

Intel® IQ80321 Evaluation Platform Board Total Flash size is 8 MB

IQ80321 Flash technology is based on Intel Strata Flash family

IQ80321 Flash uses a 16-bit interface

IQ80321 Flash utilizes the 80321 Peripheral Bus

IQ80321 May be programmed using the PCI-X interface – Flash Recovery Utility (FRU) Utility

IQ80321 May be programmed using a RAM based software target monitor – Redhat Redboot and ARM Firmware Suite

IQ80321 May be programmed using a JTAG emulation/debug device

Board Manual

35

Image 35

Intel IQ80321 manual Flash Memory Requirements

Contents

Board Manual Intel IQ80321 I/O Processor Evaluation Platform Board Manual Intel IQ80321 I/O Processor Evaluation Platform Contents Debug Interface Dram 100 119 Figures Tables 105 Description Revision History This page intentionally left blank Related Documents Document Purpose and Scope Component Reference Electronic InformationComponent References Electronic Information Definition Terms and DefinitionsTerms and Definitions Intel 80321 I/O Processor Intel 80321 I/O Processor Block Diagram Intel IQ80321 I/O Processor Evaluation Platform Feature Definition Intel IQ80321 Evaluation Platform Board FeaturesSummary of Features Power and Backplane Requirements Kit ContentHardware Installation First-Time Installation and Test Supported Tool Buckets Factory SettingsContents of the Flash Development Strategy Target Monitors Redhat Redboot ARM Firmware Suite Semihosting File I/O ARM Angel Ethernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug Communication GNUPro GDB/Insight Communicating with Redboot Intel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDB ARM Extended Debugger This page intentionally left blank Intel Functional Diagram Board Form-Factor/Connectivity Form-Factor/Connectivity Features Power Features Power Supported Dimm Types Battery BackupDDR Memory Features Memory Subsystem Flash Memory Requirements Flash Memory Requirements Intel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt Routing Intel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus Features Flash ROM Flash ROM Features Uart Uart Features HEX Display on the Peripheral Bus HEX Display Rotary Switch Requirements Rotary Switch Battery Status Buffer Requirements Battery Status Intel 82544EI Gigabit Ethernet Controller Debug InterfaceConsole Serial Port Ethernet Port Jtag Port Pin-out Logic-Analyzer ConnectorsJtag Debug 3.1 Jtag Port Mictor J3F2 Micor J3F2 Signal/Pins Mictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Mictor J1C1 Micor J1C1 Signal/Pins Mictor J3C1 Micor J3C1 Signal/Pins Mictor J2C1 Micor J2C1 Signal/Pins Reset Sources Board Reset SchemeReset Requirements/Schemes Switch Summary Switches and Jumpers Pcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation Settings Switch S7E1- 2/3 Detail Descriptions of Switches/Jumpers Switch S7E1- 6/7 Switch S7E1- 4/5 S7E1-8 Switch S7E1Switch S7E1 8 Descriptions Switch S7E1 8 Settings and Operation Mode Switch S8E1 Switch S8E1 6 Descriptions Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 8 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Descriptions Switch S8E2 Switch S8E2 1/2 Switch S9E1 4 Descriptions Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 13 Settings and Operation Mode Switch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9F1 Jumper J9E1 This page intentionally left blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device Configuration Parameter Voltages DramComponents on the Peripheral Bus DDR Memory Bias Voltage Minimum/Maximum Values Software Reference Address Read Register Write Register Uart Register Settings Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory Map Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Necessary Hardware and Software IntroductionPurpose Related Web Sites Hardware Setup Setup Software Flow Diagram Software Setup Creating a New Project New Project Setup Configuration Overview Flashing with Jtag Using Flash Programmer Building an Executable File From Example Code Debugging Out of Flash Running the CodeLab Debugger Launching and Configuring Debugger Displaying Source Code Manually Loading and Executing an Application Program Using Breakpoints Stepping Through the Code Setting CodeLab Debug Options Exploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware Breakpoints Debugging BasicsHardware and Software Breakpoints Software Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping