Intel® IQ80321 I/O Processor Evaluation Platform
Hardware Reference Section
3.8.6Mictor J2F1
Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Table 19. | Micor J2F1 Signal/Pins |
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| Schematic Signal Name | Mictor Pin | Mictor Pin | Schematic Signal Name |
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| 1 | 2 |
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| 3 | 4 |
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| 5 | 6 |
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| 7 | 8 |
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| FWE* | 9 | 10 |
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| PB_RST* | 11 | 12 |
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| HOLDA | 13 | 14 |
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| HOLD | 15 | 16 |
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| READY* | 17 | 18 |
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| BLAST* | 19 | 20 |
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| DEN* | 21 | 22 |
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| FOE* | 23 | 24 |
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| PB_CLK | 25 | 26 |
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| ADS* | 27 | 28 |
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| ALE | 29 | 30 |
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| F_A<0> | 31 | 32 |
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| F_A<1> | 33 | 34 |
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| F_A<2> | 35 | 36 |
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| F_A<3> | 37 | 38 |
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Board Manual | 47 |
