Board Manual 71
Software Reference 5

5.1 DRAM

For DDR SDRAM Sizes and Co nfigurations, see section 7.2.2.1 , table 139 of theIntel® 80321 I/O
Processor Developer’s Manual. Table 8 9 provides DDR SDRAM Address Register Definiti ons,
while this sections also contains multiple examples of Address Regi ster Programming.
See the Intel® 80321 I/O Processor Design Guide, s ection 7.1, table 16 for support ed DDR and
SDRAM configurations.
The Intel® 80321 I/O processor (8032 1) supports 2.5 V DDR memory. Table 8 8 lists the
minimum/maximum values for the DDR memory bias vo ltages:
For all registers relating to DRAM and other MCU related registers, see section 7.6, Table 149 of the
Intel® 80321 I/O Processor Developer’s Manual.

5.2 Components on the Peripheral Bus

The 80321 has a peripheral bus which contains the following periphera l devices:
•Flash ROM
•UART
•Rotary Switch
•Hex Display
Peripheral memory-Mapped Register Locations for the Peripheral Bus Interface Unit can be found in
the Intel® 80321 I/O Process or Developer’s Manual, Section 7.5, Table 298, sheet 7 of 12. The
appropriate Base address and Limit registers must be set for each of the six chip enables (PCE0-5).
Each peripheral and its corresponding PCE# are described in this section.
All registers associated with the PBI can be found in the Intel® 80321 I/O Processor Developer’s
Manual, section 8.6, table 12 8.
Table 88. DDR Memory Bias Voltage Minimum/Maximum Values
Symbol Parameter Voltages Units
Minimum Maximum
VCC25 2.5 V Supply Voltage 2.3 2.7 V
VREF Memory I/O Reference Voltage 1.15 1.35 V
VTT DDR Memory Termination Voltage VREF - 0.04 VREF + 0.04 V