Board Manual 111 | Intel IQ80321 instruction

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

C.4 Flashing with JTAG

C.4.1 Overview

CodeLab and Raven are capable of reading from, writing to, and erasing the contents of the Flash on the evaluation board. The board comes with RedBoot loaded in the Flash. RedBoot is the RedHat debug monitor which initializes the board and has some debug and diagnostic functions. It is capable of serial communication with the console of a debug program or with Microsoft HyperTerminal, and it prepares the board for accepting an application program.

CodeLab invokes a Flash programmer written by Macraigor. More information on the Flash programmer is located at:

http://www.ocdemon.net/Merchant2/merchant.mv?Screen=CTGY&Store_Code=MTS&Categ ory_C ode=Software.

This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf (executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. Worcester.i32 is an ARM BootMonitor Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is similar but not identical to RedBoot.

Macraigor offers conversion tools to convert existing file types to a supported file type. These conversion tools are located at:

C:\ATI\codelab\codelab Debug\Macraigor\Flash Programmer

The ReadMe.txt file describes the conversions tools. BinToS19.exe converts binary files to srec files and MakeIntelHex.exe converts a.out files to Intel Hex files. When using the BinToS19.exe conversion tool, use 0x0 for the starting address. For example, at the CMD prompt in the directory where BinToS19.exe is located, the command line looks like this:

C:\ATI\codelab\codelab Debug\Macraigor\Flash Programmer>bintos19

C:\temp\redboot_ROM.bin 0x0 c:\temp\redboot_ROM.s19

Board Manual

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Image 111

Intel IQ80321 manual Board Manual 111

Contents

Board Manual Intel IQ80321 I/O Processor Evaluation Platform Board Manual Intel IQ80321 I/O Processor Evaluation Platform Contents Debug Interface Dram 100 119 Figures Tables 105 Description Revision History This page intentionally left blank Related Documents Document Purpose and Scope Component Reference Electronic InformationComponent References Electronic Information Terms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Intel 80321 I/O Processor Block Diagram Intel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition Power and Backplane Requirements Kit ContentHardware Installation First-Time Installation and Test Supported Tool Buckets Factory SettingsContents of the Flash Development Strategy Target Monitors Redhat Redboot ARM Firmware Suite Semihosting File I/O ARM Angel Host Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug Communication GNUPro GDB/Insight Communicating with Redboot Intel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDB ARM Extended Debugger This page intentionally left blank Intel Functional Diagram Board Form-Factor/Connectivity Form-Factor/Connectivity Features Power Features Power Supported Dimm Types Battery BackupDDR Memory Features Memory Subsystem Flash Memory Requirements Flash Memory Requirements Intel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt Routing Intel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus Features Flash ROM Flash ROM Features Uart Uart Features HEX Display on the Peripheral Bus HEX Display Rotary Switch Requirements Rotary Switch Battery Status Buffer Requirements Battery Status Intel 82544EI Gigabit Ethernet Controller Debug InterfaceConsole Serial Port Ethernet Port Jtag Port Pin-out Logic-Analyzer ConnectorsJtag Debug 3.1 Jtag Port Mictor J3F2 Micor J3F2 Signal/Pins Micor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Mictor J1C1 Micor J1C1 Signal/Pins Mictor J3C1 Micor J3C1 Signal/Pins Mictor J2C1 Micor J2C1 Signal/Pins Board Reset Scheme Reset Requirements/SchemesReset Sources Switch Summary Switches and Jumpers User Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation Settings Switch S7E1- 2/3 Detail Descriptions of Switches/Jumpers Switch S7E1- 6/7 Switch S7E1- 4/5 S7E1-8 Switch S7E1Switch S7E1 8 Descriptions Switch S7E1 8 Settings and Operation Mode Switch S8E1 Switch S8E1 6 Descriptions Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 8 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Descriptions Switch S8E2 Switch S8E2 1/2 Switch S9E1 4 Descriptions Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 13 Settings and Operation Mode Switch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9F1 Jumper J9E1 This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device Configuration Parameter Voltages DramComponents on the Peripheral Bus DDR Memory Bias Voltage Minimum/Maximum Values Software Reference Address Read Register Write Register Uart Register Settings Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory Map Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Hardware Setup Setup Software Flow Diagram Software Setup Creating a New Project New Project Setup Configuration Overview Flashing with Jtag Using Flash Programmer Building an Executable File From Example Code Debugging Out of Flash Running the CodeLab Debugger Launching and Configuring Debugger Displaying Source Code Manually Loading and Executing an Application Program Using Breakpoints Stepping Through the Code Setting CodeLab Debug Options Exploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Hardware Breakpoints Debugging BasicsHardware and Software Breakpoints Software Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping