Intel® IQ80321 I/O Processor Evaluation Platform
Hardware Reference Section
3.9Board Reset Scheme
Figure 15 depicts the reset scheme for the IQ80321. Table 23 list the reset schemes for the IQ80321.
Table 23. Reset Requirements/Schemes
Description
Primary PCI reset, resets all devices on the board. It occurs during the
The SRST signal from the JTAG connector is a
Figure 15. | RESET Sources |
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| Switch S1H2: Push Button Reset |
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| Jumper J102 | Circuit |
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| Reset from Primary |
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| JTAG Connector | SRST Signal |
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| TRST Signal | from/to JTAG |
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| Emulator |
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| from JTAG |
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| Emulator |
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| To Intel® 80321 | |
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| TRST Pin |
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| Intel® 82544 GbE |
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| Reset | Secondary |
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| UART |
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| Intel 80321 | FLASH |
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| I/O Processor |
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| Note: SV - Supervisory |
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Board Manual |
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