Board Manual 53
Intel® IQ80321 I/O Processor E valuation Platform
Hardware Reference Section
3.10.2 PCIX Initialization Summary
Figure 16 shows a routing guidance on how PCI-X m ode is determined/implemented on the
secondary side of the PCI- X bridge. The Intel® 80321 I /O processor (80321), G bE device, and the
PCI-X expansion slot all res ide on this bus.

3.10.2.1 User Defined Switches

User can set the PCIXCAP signal to force one of the following modes:
The IQ80321 platform is by de fault set to operate this bus in P CI-X 66 MHz mode. The lo ading on
the secondary PCI-X bus may result in marginal operation when speed is greater than that.
When an expansion card is placed on the PCI-X expansion slot, the mod e is based on the least
capable device on the bus. For example, when the bus is forced to be PCI-X 66 capable and then
places a PCI 66 card in the expansion slot, then the bus is configur ed as PCI 66.
Important: The clock selection is manually configured. Pay close attention to setting this up correctly.
Important: All settings must be done prior to power-up/reset.

3.10.2.2 PCI-X Bridge Initialization Signals

The On-board PCI-X bridge samples the PCIXCAP, SEL100, and M66EN signals to drive/indicate the
correct mode to the secondary bus devices. The 80321 uses these signals to set its internal PLs,
providing correct frequency to the Intel® XScale™ core, as well as internal, peripheral, and DDR buses.
Figure 16. PCI-X Routing Diag ram on Second ary PCI-X Bridge
Swit ch
Clock
Multiplier/Bu ffer
PCI-X
Bridge
PCIXCAP M66ENSelectionEnable
PCI-X Clock
33 MHz
66 MHz
100 MHz
133 MHz
SPCI-X Slot
82544
Gigabit Ethernet
Sel 100
Initializatio n
Signals
PCIXCAP
M66EN Signal
S_DEVSEL
S_FRAME
S_IRDY
S_STOP
S_TRDY
Switch
Intel®
80321 I/O
Processor
S7E1-6 S7E1-7S7E1-8
Switch
S8E2-1 S8E2-2
Swit ch
S8E1-4
Swit ch
S8E2-4
OSC
PCI-X 100/133 PCI-X 66 PCI