Intel® IQ80321 I/O Processor Evaluation Platform
Hardware Reference Section
3.8.9Mictor J2C1
Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Table 22. | Micor J2C1 Signal/Pins |
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| Schematic Signal Name | Mictor Pin | Mictor Pin | Schematic Signal Name |
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| S_FRAME* | 1 | 2 | S_ACK64* |
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| S_DEVSEL* | 3 | 4 | S_REQ64* |
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| S_TRDY* | 5 | 6 | S_CLK0 |
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| S_C/BE<2> | 7 | 8 | S_C/BE<4> |
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| S_C/BE<3> | 9 | 10 | S_C/BE<5> |
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| 11 | 12 | S_C/BE<6> |
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| S_REQ* | 13 | 14 | S_C/BE<7> |
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| S_GNT* | 15 | 16 | S_C/BE<0> |
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| S_RST* | 17 | 18 | S_C/BE<1> |
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| INTD* | 19 | 20 | S_SERR* |
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| INTC* | 21 | 22 | S_PAR* |
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| INTB* | 23 | 24 | S_PERR* |
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| INTA* | 25 | 26 | S_LOCK* |
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| 27 | 28 | S_STOP* |
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| 29 | 30 |
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| 31 | 32 |
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| 33 | 34 |
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| 35 | 36 | PWRDELAY |
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| 37 | 38 | VTT_DDR |
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50 | Board Manual |
